Using the latest forward error correction (FEC) codes can achieve ever lower bit error rates. But the march towards Shannon's limit comes at a price - increased computational complexity. Today's FEC decoders make complex calculations, and must often perform numerous iterations. In addition, the proliferation of adaptive coding and modulation schemes often requires a decoder that can handle dozens or even hundreds of individual modes. Such tasks are well-matched to the flexibility and processing power found in Star Communications' PVP and PCA cards.
The figure shown here illustrates a typical turbo decoding implementation using FPGA technology. Processing steps are implemented using logic resources of the FPGA, shown in yellow. Storage is implemented using block RAM resources of the FPGA, shown in blue. In addition to the decoding algorithm shown (maximum a posteriori, or MAP), FPGA technology is also a good choice for implementing log-likelihood ratios, belief propagation, and the many variations of the sum-product algorithm common in low density parity check (LDPC) decoders. This is true whether the codes are regular or irregular, protograph-based, or based on Euclidean or projective geometry.
Whether you need to utilize basic algorithms such as Viterbi or Reed-Solomon decoding, or the most advanced Turbo, low density parity check (LDPC), or other more recent codes, a PVP or PCA card can handle the job easily!